Non-volatile memory devices are used in applications requiring the storing of information that has to be retained even when the memory devices are not powered. Generally, each memory device includes a matrix of memory cells based on floating gate MOS storage transistors. Each storage transistor has a threshold voltage that may be set (according to an electric charge in its floating gate) to different levels representing corresponding logic values. For example, in Electrical Erasable and Programmable Read-Only Memories (EEPROMs), each storage transistor may be both programmed (by injecting electric charge into its floating gate) and erased (by removing electric charge from its floating gate) individually. A set of MOS selection transistors applies the required voltages selectively to the corresponding storage transistor (with a quite complex structure that limits the capacity of the EEPROMs to a few Kbytes). On the other hand, flash memories have a simple structure that allows obtaining very high capacities thereof, up to some Gbytes. The memory cells are grouped in sectors where each cell is integrated in a common well of semiconductor material without any selection transistor (with the need of erasing the flash memories at the sector level).
In both cases, a production process of the memory devices substantially differs from a standard one (for example, in CMOS-technology). Indeed, the storage transistors may require an additional polysilicon layer to define their floating gates (besides the one used to define their control gates as in the CMOSs). This difference may add design complexity, which may significantly increase the manufacturing cost of the memory devices (of the order of 30% with respect to standard CMOS devices).
Single poly EEPROM, also referred sometimes a few time programmable FTP memories, have been proposed in the last years that overcome some of these issues. In single poly memories, the memory cells are again grouped in sectors (integrated in corresponding wells). However, the storage transistor of each memory cell now has a distinct control gate region being capacitively coupled with its floating gate. Therefore, the FTP memories use a single polysilicon layer, so that they may be manufactured with the standard CMOS production process.
However, such processes and designs typically result in poor reliability. In order to target a higher level of reliability in non-volatile memory design, differential cell design may be used. However such designs are not sufficient by themselves. Therefore, additional checks on logic data, for example, a CRC code or a more effective Error Correction Code ECC (SEC/SED) can been added. CRC inserts a certain level of improvement with respect to a standard differential mode, and in any case is typically poor and increases the memory area significantly.
On the other hand, an ECC approach requires different levels of customization and therefore impacts memory architecture. ECC code is typically stored in spare area requiring extra storage space. Specifically, ECC impacts the digital block memory area because of specific algorithms that have to be implemented. ECC also results in poorer performance (e.g., access time) because of data post processing at digital level. For example, during a programming operation, the ECC unit calculates the ECC code based on the data stored in the sector. The ECC code for the data area is then written to the corresponding spare area. When the data is read out, the ECC code is also read out, and the reverse operation is applied to check that the data is correct. It is possible for the ECC algorithm to correct data errors. The number of data errors that can be corrected depends on the correction strength of the algorithm used.
In particular, because of the slower access times and the specific algorithms that have to be implemented, typically ECC cannot be implemented in small memory IPs because complex digital Nock for data managing may be required that could be not compatible with the simple and area effective target of small memories, which typically are serial memories with few gates for internal state machine to manage basic operations.